Electronic devices, including mobile and portable devices such as cell phones, personal digital assistants (PDA), and digital cameras, use static random access memory (SRAM) chips with a high storage density. In deep submicron technology, a large number of SRAM cells are used in products such as microprocessors, communications chips and system on a chip (SOC) applications. One ongoing goal is to reduce the size of each cell in order to lower overall costs.
FIG. 1 shows a schematic diagram of a conventional six-transistor (6T) SRAM cell 10. In this cell, a first inverter includes p-channel transistor 12 coupled in series with n-channel transistor 14 and a second inverter includes p-channel transistor 16 coupled in series with n-channel transistor 18. For each transistor in the figure, the source, drain and gate is labeled with the reference number of the transistor followed by an “S,” “D,” or “G,” respectively. The two inverters are cross-coupled so that the gates of transistors 12 and 14 are coupled to the source regions of transistors 16 and 18 (which make up the second storage node 26) and the gates of transistors 16 and 18 are coupled to the source regions of transistors 12 and 14 (which make up the first storage node 24). The drains of transistors 12 and 16 are coupled to a high supply voltage node (e.g., Vcc or Vdd) and the drains of transistors 14 and 18 are coupled to a low supply voltage node (e.g., Vss or ground).
Transistors 20 and 22 provide access to the cross-coupled inverters. Accordingly, the transistor 20 has a current path coupled between a first storage node, in this case, the source regions of transistors 12 and 14, and a bit line BL. The transistor 22 has a current path coupled between a second storage node, in this case, the source regions of transistors 16 and 18, and a complementary bit line BL/. The gates of the transistors 20 and 22 are coupled to wordlines WL and WL′. If the wordlines WL and WL′ are not formed from a continuous level of conductive material, the cell is referred to as a split wordline (SWL) architecture. In any event, the wordlines WL and WL′, and therefore the gates 20G and 22G, are coupled together functionally, e.g., in a separate level of metal.
During operation, data is written into the cell 10 by activating the wordline WL (and WL′) to couple the first storage node 24 to the bitline BL and the second storage node 26 to the complementary bitline BL/. The value of the data carried on the bitline BL will be of the opposite value of the data carried on the complementary bitline BL/ and the cross-coupled inverters will latch that value. For example, if a logical “1” is applied to the first storage node 24, the inverter 12/14 will generate a logical “0” and apply that to the second storage node 26. At the same time, the inverter 16/18 will invert the logical “0” and apply a logical “1” to the first storage node 24. This state will be held until new data is applied through the access transistors 20 and 22 (or power is removed).
FIG. 2 shows a layout of an SRAM cell of the prior art. Each of the regions has been labeled to correspond to the schematic diagram of FIG. 1. In this implementation, the source regions 12S–22S and drain regions 12D–22D are implemented in heavily doped silicon and the gates 12G–22G are implemented in doped polysilicon. Metal is used for the interconnects WL, BL, Vss, Vcc, BL/ and WL′. Contacts between the silicon or polysilicon and overlying metal are indicated by the symbol showing a square with an “X” in it. In this architecture, the cell uses ten such contacts. The cell also makes use of three levels of metal (referred to as metal 1, metal 2, and metal 3, with metal 1 being closest to the silicon body and metal 3 being furthest from the silicon body). In one scheme the first metal layer is used as an intra-cell local interconnect (12S to 14S and 16S to 18S) and as landing pads (e.g., Vss, Vcc, WL and BL) and the second metal layer as the wordline conductor, and as landing pads (e.g., Vss, Vcc and BL). The third metal layer can be used for the bitline conducts (BL, BL/) and reference voltages (Vcc and Vss). In a second kind of layout scheme the first metal layer can be used for intra-cell local interconnects (12S to 14S and 16S to 18S) and landing pads (e.g., Vss, Vcc, WL and BL) and the second metal layer can be used for the bitline (BL and BL/) and one power supply (e.g., Vcc). The third metal layer can be used for the wordline and Vss conductor lines.
FIG. 3 shows another layout of an SRAM cell of the prior art. As before, each of the regions has been labeled to correspond to the schematic diagram of FIG. 1. The implementation of FIG. 3 differs from that of FIG. 2 in that the contact 28 between the polysilicon that forms gates 16G and 18G and the doped silicon that forms region 12S is a butted contact (as indicated by the rectangle with an “X” in it.) A butted contact 28′ is also used between the polysilicon that forms gates 12G and 14G and the doped silicon that forms region 16S. Butted contacts are disclosed in U.S. Pat. No. 5,955,768, which is incorporated herein by reference. This implementation is advantageous over of the implementation of FIG. 2 since the number of contacts has been reduced from ten to eight (six contacts and two butted contacts).